The present invention relates generally to digital logic circuits and, more particularly, to level shifter circuits for shifting a digital signal between two voltage levels.
Digital logic circuits are widely used in the areas of electronics and computers. However, with advances in circuit technology, the various digital logic circuits that communicate with one another may operate at different power supply voltages. For example, a digital integrated circuit may include an input/output (I/O) section that operates at a first logic level, and a central logic core that operates at a second, lower supply voltage, since operating at the lower voltage reduces power consumption. On the other hand, the supply voltage for the I/O section must be kept at a higher supply voltage than the logic core to ensure a higher signal to noise ratio. For example, the I/O section may operate at supply voltages ranging from 3.3V to 5V, while the logic core operates at 0.5V to 1.5V. Therefore, an interface is required to ensure smooth communication between different digital logic circuits operating at different voltages.
In particular, an interface is required that allows a shift in the voltage of a digital signal from a low supply voltage (VDD) level to a higher supply voltage (VDDa) level. This voltage level shifter acts as an interface between a chip or circuit operating at the low power supply voltage (VDD) and a chip or circuit operating at the higher power supply voltage (VDDa). The conventional voltage level shifter is included as a part of the chip operating at VDDa. This level shifter requires both supply voltages, VDD and VDDa, for its operation.
The conventional level shifter has limitations since it operates on dual supply voltages, i.e., both VDD and VDDa. Consequently, during the fabrication of the level shifter, connections to both VDD and VDDa are required. Extra connections lead to a congestion in the circuit layout, as well as extra pin counts. Hence, the effectiveness of the level shifter is reduced. Currently, the above-mentioned limitations are overcome by using a larger chip area, but this leads to an increase in fabrication cost. Alternatively, there is a compromise in the performance to reduce the cost.
Hence, there is a need for a level shifter that does not require dual supply voltages, and that reduces layout congestion and pin count.